Project title: ANALOG & MIXED-SIGNAL BOUNDARY-SCAN TESTABILITY TECHNOLOGY

Company name : TESTABILITY LTD.

TECHNOLOGICAL FIELD
Electronic boards and devices, Testing,
Design-For-Testability

KEY WORDS
Electronic Analog Testing,
Printed Circuit Board (PCB), Boundary-Scan (JTAG) Technology,
Design-For-Testability (DFT), Integrated Circuits (IC), ASIC

PROJECT SUMMARY
TESTABILITY LTD. has developed a new testability enhancement
technology, BFT (Bridge-For-Testability) that is implemented in
the new ASIC named BFT and in the BFT intellectual property (IP)
for implementation in any integrated circuits (IC) or ASICs with
the use of analog Boundary-Scan features. The company is
launching this technology to its target market of electronic
hardware testability tools.
With its new BFT device, Testability Ltd. will be able to provide
the framework for high level testability development and
implementation in electronic board design using both the analog
and digital Boundary-Scan (JTAG) technology. Testability plans to
develop a complete line of testing devices.
The use of the new BFT device(s) and/or BFT IP inside different
ICs will enable testers to:
* reach the best possible access for virtual in-circuit analog
and digital electronic probing and passive elements measurement
in mixed-signal printed circuit boards through standard
Boundary-Scan protocol without using the true in-circuit testers
(ICT) or manual probing
* provide a unique opportunity for easy, qualitative, and
low-cost testability upgrade of the existing assembled printed
circuit boards
* bring improved test coverage, leading to better product yields
and lower costs, reduced field returns and increased printed
circuit board end-user satisfaction.

ADVANTAGES
The key benefits of the new BFT device(s) and/or BFT IP at the
mixed-signal printed circuit board debug and manufacturing phase,
as well as at the field service phase are:
* test development time savings
* simplified debug without knowing of the board under test
functioning
* access in high density and poor-access boards without physical
probing
* improved fault coverage and diagnostics of the board under test
* shortened diagnostic time and improved test throughput through
reduced test time
* minimal design changes
* lower cost and more productive automatic test equipment (higher
throughput)
* quick field testing of both structural and functional faults
down to the component level
* reduced board and system downtime

ENTREPRENEURS
Dr. Ami Gorodetsky - Chief Scientist,
test and DFT issues expert
Mr. Azi Machtiger - General Manager,
experienced ASIC developer

PROJECT STATUS
The project started its incubator period in 2004.

COOPERATION REQUIRED
Financial investors, strategic partners, joint ventures.
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TEL: 972-2-9963880 (ext.403) FAX: 972-2-9961571 E-MAIL:
amigo@TestabilityScan.com

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